Data communication system employing an asynchronous start-stop clock generator



Feb. 25, 1969 R. E. MILFORD 3,

DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Filed m 19, 1965 Sheet of 18 READER l llfi fi ra mguc UNCH mffi f 24b 7 4 Oh if. 5 oarAsr DATA SET 25 CENTRAL PROCESSOR INVENTOR.

RICHARD E. MILFORD ATTORNEY R. E. MILFORD Feb. 25. 1969 DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Sheet Filed May 19, 1965 mwodwm 0-90- JOEZOU Lao-Z3528 commuuomm 4 mhzmu WONN ma W 5.6.8:. to m :25. 5.669. Kim 5. 52% t W 0N 28 6Ez8 505:. 6

Feb. 25, 1969 R. E. MILFORD 3,430,204

DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLQCK GENERATOR Filed may 19, 1965 Sheet 3 of 1a A STOP m BITS tiiagaismiz i5: 1 5 H.|||| 1|| IDATA en's TINVERSE RE- DUNDANT en's START DUMMY DUMMY ST P CHARACTER FRAME Feb. 25, 1969 R. E. MILFORD 3,430,204

DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Filed May 19, 1965 Sheet 4 of 1s TERMINAL CONNECTORS BUS'NESS MACHINE LINE KINTO INTER Lock KmT| JDNT Q 40 7O; |8V

1)-r |av T0 J 56 REAIER PUNCH 75 -24v JJ o 68 "7 DATA 551- 8 1 H READERE UNCO-i RlNGI :1 DATA SET Q A I REMOTE 44 Q i as CONTROL DATA SET W116 o SSH-H READY snewu.

Fans 2 4on2 62 TO mm SET m e m owcn RELAY RELAY RELAY mm KIN 1e KPWR 1 av ov ov g;

Feb. 25, 1969 R. E. MILFORD 3,430,204

DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Filed May 19, 1965 Sheet .5 of 18 on 9 o e1 A. OFF 92 93 B7 REQUEST FRSDI TO SEND CARRIER 59 2 0N-oFF s I JONDO man 34 I00 DELAY FPUTO moo mm DUPLEX S I ODE S'GNAL EDGE 95 FDPX as A0 DDCRI R o FDPXO DGE I (SIGNAL n2 IOI FXMEI L 9L H4 5 READER Fcozo sec. "01' FREV REvERsE 4 DELAY {52 36 J FXME DcoDo SPACE O L cp (MARKER CLEAR LEAD R o we TO SEND FTRDI M EDGE KINTO FBFx a CLOCK GENERATOR ,IMDAI DMRm 20o DMRKI DTCP FDPXO 0 ms I57 T T2 o 0 mo D DMRKO OKINTO Igan' arr FCOOI PERIOD PERIOD Q---- DCTIO ucolo FCOII O- gg l W O-- 201 Feb. 25. 1969 Filed May 19, 1955 BIT COUNTER FCOBI R. E. MILFORD DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-$TOP CLOCK GENERATOR sneet or18 \I\ 0 N 6 O H.

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TTX3I Feb. 25, 1969 R. E. MiLFORD DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Sheet 7 of 18 Filed May 19, 1965 2 Q I n N- .nxhL. 44206 500. 44206 cub-Z300 tm :QQm A4203 55.2300 .20

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FeB. 25, 1969 R. E. MILFORD DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Sheet 9 of 18 Filed May 19, 1965 Now 53E 20E $3128 55% a. f c .1 59mm 2 55mm .525 Emu 8E amu m 25 6 E95 .002. Emma 03E 0 63a t 8 .SE .85 wwmm l HHMUU B 05; f 82: 85. o 656 BE n 939. amt

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Sheet /0 0118 FLOW CHART OF READ OPERATION RESET FSRH on I6 COUNT.

YES

SEXJARE m HIBIT P as TRAIIsIIIIT.

I STARTCLOCK RESET TEST FoR SET RESET cowum s. FLIP-FLOP FLIP-FLOP GENERATOR. FREV. FDPX.

I & YES I SET TAPE vs 30 SET FLlP- SET FLIP- LEADER FLIP I. DELAY FLOP FLOP -FLOP FTLD. FMOB. FTRD.

3 18;?" s; CH FLIP FF 5%:

'TRAusIIIIT 'R EAD EA 0K READ ZE QQZP FIRsT ZERO one BLOCK CHARACTER. COMPLETE OF 0005, OF mm.

is Oil-A sTART RI-3ET RESET SEARCH CLOCK FLIP- FLOP FLIP-FLOP COMPLETE? mos. FTRD.

YES

TRANSFER TRANSMIT RESTART DATA To 2ND ZERO CARRIER 5|-||FT REG, OF 00E. EXCHANGE.

INHIBIT 5; FRoIII TAPE s LEAD ER 7 YES RESET FLIP- FLOP L'NE. DATA se FRSD- I CARRIER STOPS.

Feb. 25, 1969 R E. MILFORD DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNGHRONOUS START-STOP CLOCK GENERATOR Filed May 19, 1965 TRANSMIT ZERO CODE FCOSI s'rm'r MARK -v 7 i l l I w H 1 sPAcE TRANSMlT FLIP- FLOP FREVO :2; oclso FSHII I52 Sheet of 18 l l I 2 STOP BITS FX MT DTCXO ELDI 00 6| DZLO DTZRI J M049 Fsmo 001 o F0030 #55 use FSHH FCOSI OCQIO RCO 3,430,204 EMPLOYING AN ASYNCHRONOUS Sheet /2 of 18 Feb. 25, 1969 R. E. MILFORD DATA COMMUNICATION SYSTEM START-STOP CLOCK GENERATOR Filed May 19, 1965 Oummo .Imm. 51k. 660 EmOn OmOOo :FUQ mw.r BOO- 500m :00- 68. ONOUO 9000 2x00 Ohmuc Feb. 25, 1969 R. E. MILFORD 3,430,204

DATA CQMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Filed May 19, 1965 Sheet /3 of 18 START FLOW CHART FOR PUNCH OPERATION q P TART CLOCK RECEIVE RECEWE 55] mp; Z uupucms numcma FPWB AT CHARACTER. CHARACTER. l6 c1.

7 PUNCH PUNCH RECE VE (E1- SECOND CHARACTER BREY. ZERO cone.

i SET YES START FLIP-FLOP ERROR? PUNCH.

FPu1:

no RECEIVE $|GN3A|L 'fDTP gap- PUNCH TTS R CHARACYER GENERATED COUNT l. COL-a RESET HOLD PM RESET FLIP-FLOP REGISTER FLIP- FSTE RESET. FPUT.

YES IS FLIP- FLOP FERR SET? SET INHIBIT FLIP-FLOP RETURN FSTP. CARRIER.

PUNCH SEND SPROCKET RETURN ONLY. CARRIER.

WAIT

ART.

TO PUNCH REGISTER.

Feb. 25, 1969 R. E. MILFORD DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Sheet /4 of 18 Filed May 19, 1965 ommwu wmJDm 300 6 u w 025E A Onmkk .r

Feb. 25, 1969 R. E. MILFORD 3,430,204

DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Filed May 19, 1965 Sheet /5 of 1s FERRI FERRO D Tl DDCRI KINTO QCQLO ERROR PUNCH LOGIC R. E. MILFORD Feb. 25, 1969 Sheet /6 of 18 Filed May 19, 1965 $223 50 1022 Oh 102R 2 nziqjou NZEDJOO 2022 OF :02? Oh o m 0 ml! 0 0 mill &8 g z SE5 2?. .21 2t 2c in. 21 N2. :1 m m. m m m m :5. 6st :5. 31E 5%. :ifi $5. 6.5 :12 i=8 a Feb. 25, 1969 R. E. MILFORD 3,430,204

DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Sheet Filed May 19, 1965 503m :ozE 52m Zzma Ehwm l EEI. .EE 1 T 5:2 L T 6E6 Fxmu .uxwu .nImm

ONOOG 0600'... D206 2min 0.0-! BE :9 m 0 h wn n muPO m IO PmmE ucOu OmmN hwy-E Feb. 25, 1969 DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS Filed May 19, 1965 TIMING CHART END OF BLOCK DMRKI START-STOP CLOCK GENERATOR FSTPI R. E. MILFORD DPROI DENAI FPWBI FWOSI United States Patent 3,430,204 DATA COMMUNICATION SYSTEM EMPLOYING AN ASYNCHRONOUS START-STOP CLOCK GENERATOR Richard E. Milford, Phoenix, Ariz., assignor to General Electric Company, a corporation of New York Filed May 19, 1965, Ser. No. 457,018 U.S. Cl. 340-1725 10 Claims Int. Cl. Gllb 13/00; H04l 5/14 ABSTRACT OF THE DISCLOSURE A data communications system employing a clock generating means which starts and stops periodically in response to information signals, the period of time being short enough so that resynchronization is not necessary during the period of time it is operating.

TABLE OF CONTENTS Column General Description Statement of the Invention.-. Brief Description of Drawings.. Glossary and Index of Signals. Data Communication System Oper Line Direction ControL- Data Transmit Sequence Data Receive Sequence. Transmission or 5, 6 and 7 Level Codes. Error Detection Tape Operating Parameters Block of Data End-oi-Data-Block Marker Data Sets Descri tion- Atten ed Data Set Operation--. Unattended Data Set Operation-. Logic Components Flip-Flop. AND-Gate..-

0 R-Gate. Inverter Communication Control Request to Send Data... Establishing Communication... Terminating Communication- Communication Interrupts Clock Generator and Bit Counter Shift Register Description of Read Tape Mode of Operation. Set 'Iape Read Flip-Flop FIRD- Start Clock Generator Transmission of First Code.

Set Tape Leader Flip-Flop FT Start Reader Search End-oi-Block Recognition- Read Termination Functio Retransmission of Data Description of Punch Tape Mode of Operation. Receipt of First Zero Code Receipt of Non-Zero Character- Error Circuitry End-oi-Block column 8 punch. Claims GENERAL DESCRIPTION Statement of the invention This invention relates to data communication systems and more particularly to systems for asynchronously generating groups of clock pulses.

Digital information has been transmitted from one location to another by means of electrical signals which have some characteristic such as frequency, duration or amplitude varied to indicate the information content. Where the digital information is in binary form, each individual digit or bit of digital information is allotted one of a number of recurring equal intervals, called bit intervals, during which the signal characteristics or changes therein signify the specific bit of digital information. The digital information may be derived by determining which of the signal characteristics are within each bit interval. Binary digital information is normally represented by varying a signal characteristic between first and second values or by varying the signal in a first or second sense.

Many codes are used for representing binary digital information. One binary code may indicate a digit value of one by the presence of a change of state during some portion of a bit interval and a digit value of zero by the absence of a change of state during a bit interval. Another binary code may represent a digit value of one by a first potential level during a bit interval and a digital value of zero by a second potential level during a bit interval.

It is possible with binary type codes to represent a great number of sequential bits of binary information without any change in the signal, i.e., a sequence of bits each having a zero digit value representing a constant potential level. Consequently, it is necessary for a system which is to receive binary digital information to have some means for determining the bit interval in order to derive the binary digital information from the transmitted signal. If the bit interval or its rate of recurrence which is termed the bit repetition rate is known, the number of binary digits which occur within any specified period is also known, but the instant during which a signal characteristic has information significance must be determined.

A data communication system which is adapted to receive digital information signals is equipped with circuitry for generating a train of pulses called clock or timing pulses at the bit repetition rate of the transmitted information signals and circuitry for utilizing the clock pulses to derive the digital information from the information signals. Synchronization must be achieved between the information signals and the clock or timing pulses and this must occur substantially instantaneously or a great deal of information may be lost before clock pulses become available at correct times to indicate the meaning of the information signals.

Many prior art systems include networks for deriving a control signal from the information signals for operating a clock pulse generator for producing clock pulses. However, these networks normally have fixed time constants which maintain the time required for synchronization constant even though the bit repetition rate varies or the repetition rate between sequentially received groups of information signals representing data characters varies. This is particularly true in data communication systems where the sequentially received characters are received asynchronously. If the data characters represented by information signals are received asynchronously, the prior art timing arrangement must be resynchronized periodically with an attendant loss of digital information each resynchronizing cycle.

Therefore, a need exists for a start stop generator for generating groups of clock pulses which last for a predetermined time, for example, the duration of one or more characters forming a character frame. A character frame usually comprises a start bit followed by a plurality of intelligence bits followed by two or more stop bits. As used herein a character frame consists of one start bit followed by 7 intelligence bits forming a character, 7 intelligence bits forming the inverse image of the character and two or more stop bits.

In order to provide positive synchronization between the information signals and the clock pulses without error it was determined that the clock generating means should start and stop periodically in response to information signals. The period of operation of the clock generator should be of a short duration so that resynchronization is not necessary during the period of time it is operating.

Therefore it is an object of this invention to provide an improved data communication system employing an asynchronously operable start-stop pulse generator.

Another object of this invention is to provide a system capable of synchronizing generator clock pulses with information signals in the shortest possible time.

A still further object of this invention is to provide a synchronous clock pulse generator system capable of responding to signals which may carry information in a number of different binary codes.

A still further object of this invention is to provide a synchronous clock pulse generator system which will generate clock pulses at an established repetition rate only during the time information signals are being received.

A still further object of this invention is to provide a system for initiating transmitting character cycles as soon as a character is available from an asynchronously operating reader structure.

Further objects and advantages of the present invention will become apparent to those skilled in the art as the description thereof proceeds.

Brief description of drawings The present invention may be more readily described by reference to the accompanying drawings in which:

FIG. 1 is a simplified block diagram of an information processing system for transferring information from one location to another via common or private carrier wire lines, cables or cable carrier facilities and embodying the invention;

FIG. 2 is an expansion of the block diagram of FIG. 1 showing information flow in the system of the present invention;

FIG. 3 is a diagrammatic illustration of a 7 bit character frame;

FIG. 4 is a diagrammatic illustration of a 5 bit character frame;

FIG. 5 is a fragment view of an operating tape containing a repetition of one character followed by an Endof-Block code signal;

FIG. 6 is a simplified block diagram of the data sets shown in FIGS. 1 and 2;

FIG. 7 is a schematic illustration of the relay latching arrangement of the data set shown in FIG. 6;

FIG. 8 is a schematic block diagram of the communication control logic shown in FIG. 2;

FIG. 9 is a schematic block diagram of the clock generator portion of the clock and bit counter block shown in FIG. 2;

FIG. 10 is a schematic block diagram of the hit counter portion of the clock and bit counter block shown in FIG. 2;

FIG. 11 is a diagrammatic illustration in chart form of the clock and timing signals provided by the clock and hit counter logic shown in FIGS. 2, 9 and 10;

FIG. 12 is a schematic block diagram of a shift register;

FIG. 13 is a simplified block diagram of the reader control logic shown in FIG. 2;

FIG. 14 is a flow chart of the read operation of the structures shown in FIGS. 1 and 2;

FIG. 15 is a diagrammatic illustation of a zero code;

FIG. 16 is a simplified block diagram of the Transmit Serializer fiipfiop logic;

FIG. 17 is a diagrammatic illustration in chart form of the timing and logic signals involved in a tape reading operation;

FIG. 18 is a flow chart of the punch operation of the structure shown in FIGS. 1 and 2;

FIG. 19 is a simplified block diagram of the punch control logic shown in FIG. 2;

FIG. 20 is a simplified block diagram of the error punch logic;

FIG. 21 is a schematic block diagram of the punch register;

FIG. 22 is a diagrammatic illustration in chart form of the timing and logic signals involved in a punch operation; and

FIG. 23 is a diagrammatic illustration in chart form of the timing signals provided by the punch control logic for the End-of-Data Block recognition.

GLOSSARY AND INDEX OF SIGNALS In order to more readily understand the disclosed invention, the signals provided by the various system circuit elements are tabulated below.

Signals: Description of signals DC09 Count 9 in hit counter.

DC16 Count 16 in hit counter.

DC86 Count 8 or 16 in hit counter.

DCOD CarrierOif delayed A second.

DCST Clock generator start.

DCTl Count 1 in hit counter.

DDSC Reader delayed search complete.

DDCR Carrier On leading edge signal.

DENA Enable input to punch register.

DEND End punch tape mode.

DEOB End-of-Block code.

DMRK Receive Data-mark bit.

DOND Carrier On delayed.

DPRO Punch in Process.

DPUZ Punch zero or blank tape.

DSET Serial input to shift register.

DSPP Start punch process.

DSRE Reset pulse to shift register.

DSSR Set Start Search flip-flop.

DTCP Tape Read and Clear to Send pulse.

DTCX Tape Read and Clear to Send signal.

DTZR Tape Zero.

DXMO Retransmit.

DXMT Transmit Data to data set.

DZEl Zero code from read amplifiers.

DZER Zero code in shift register.

DZLC Tape Zero and leader.

FC(00 03) Bit counters 1 through 3.

FDPX Half-Duplex Control flip-flop.

FERR Error flip-flop.

FPUT Punch Tape Mode flip-flop.

FREV Reader Reverse flip-flop.

FRSD Request to Send flip-flop.

FSH(1-7) Shift register stages 1 through 7.

FSHE Shift Register Error flip-flop.

FSRH Start Reader Search flip-flop.

FSTP Start Punch Control flip-flop.

F'IRD Read Control flip-flop.

FW(01-08) Puch Register flip-flops for columns 1 through 8.

FXME Transmit Data Memory flip-flop.

FXMT Transmit Serializer flip-flop.

JCTS Clear to Send from data set.

JDSC Search Complete from reader.

IDRl Data set Ring Line 1.

JDRZ Data set Ring Line 2.

IDNT Energize Interlock (off-line switch).

JMDA Data set Receive Data.

INPT No paper tape signal from punch.

JOND Carrier On signal from data set.

IPUP Punch in Process.

JRS(1-8) Reader signals for columns 1 through 8.

JREC Reader eject complete.

KINT Interlock relay.

KRIN Ring relay.

QCQl Ungated Clock Generator signal.

QCQ2 Gated Clock Generator signal.

QCXl Start Clock Generator signal.

SCIN Carrier Initiate signal from Request to Send switch.

TTS3 Signal from multivibratot.

'ITX3 Pulse signal. 

